It has been the trend to scale down the sizes of memory cells to increase the integration level and thus memory capacity of a DRAM chip. As the size of DRAMs is decreased, the overlay margin between a storage node contact and a bit line for a capacitor over bit line (COB) process is reduced. This reduction in the overlay margin creates a potential for a short between the storage node contact and the bit line.
Previous methods that have been used to solve this problem resulted in additional mask layer(s) or increased topography height. Therefore, there is a need for a method for manufacturing a DRAM cell that reduces or eliminates the potential for a short, while reducing the number of mask layers used and reducing the topography height.